1. Field of the Invention
The present invention relates to a semiconductor device, and in particular to a semiconductor device including a lateral power device.
2. Description of the Background Art
Power IC (Integrated Circuit), which include power elements allowing a large current and having a high breakdown voltage as well as their drive circuits and protection circuits integrated integrally with the power elements, will be the mainstream of power elements hereafter. It is preferable to perform gate driving in such a power element by a system of a voltage control type using an insulated gate electrode (MOS (Metal Oxide Semiconductor) gate). In this voltage control type, the gate driving requires a smaller current compared with a current driving type.
Among integrated circuits (ICs) each including a plurality of semiconductor elements integrated on a single semiconductor substrate, ICs including high breakdown voltage elements are called power ICs. High breakdown voltage elements generally include MOS gates such as power MOSFETs (Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors), and such elements are achieved by RESURF (Reduced Surface Field) technologies.
The RESURF technology which was named by Apple Corporation and others in 1979 is essentially the same as the offset gate technology which is used for accomplishing the lateral MOS transistor with a high breakdown voltage.
A conventional semiconductor device will be described below as an example of a structure for achieving a level shift function with a high breakdown voltage pch-MOSFET having the RESURF structure.
FIG. 20 is a plan schematically showing a structure of a conventional semiconductor device. FIG. 21 is a schematic cross section taken along line D-D' in FIG. 20.
Referring to FIGS. 20 and 21, n.sup.- epitaxial layers 103a and 103b are formed at a surface of p.sup.- silicon substrate 101 and are spaced from each other with a p-type isolation diffusion region 105 therebetween. Each of n.sup.- epitaxial layers 103a and 103b is surrounded at the surface of silicon substrate 101 by p-type isolation diffusion region 105, so that n.sup.- epitaxial layers 103a and 103b form a high breakdown voltage pch-MOSFET formation region and a high breakdown voltage island region, respectively.
A pch-MOSFET with a high breakdown voltage is formed at n.sup.- epitaxial layer 103a which is the high breakdown voltage pch-MOSFET formation region. The high breakdown voltage pch-MOSFET has a p-type diffusion region 111 forming a source, a p-type diffusion region 113 forming a drain, a gate insulating layer 115 and a gate electrode layer 117. Source region 111 and drain region 113 are formed at a surface of n.sup.- epitaxial layer 103a with a space between each other. In particular, drain region 113 is formed of a two-layer structure including a relatively lightly doped p.sup.- diffusion region 113a and a relatively heavily doped p-type diffusion region 113b. A gate electrode layer 117 is formed on a region, which is located between source region 111 and drain region 113, with gate insulating layer 115 therebetween.
An n.sup.+ buried diffusion region 107a located immediately under source region 111 is formed between n.sup.- epitaxial layer 103a and p.sup.- silicon substrate region 101.
The high breakdown voltage pch-MOSFET has a track-like form in a plane as shown in FIG. 20. More specifically, drain region 113 formed at the surface of substrate 101 surrounds source region 111 with a predetermined distance therebetween.
At a central region surrounded by source region 111 having a track-like planar configuration, there is formed an n.sup.+ diffusion region 121 adjoining to source region 111.
At n.sup.- epitaxial layer 103b forming the high breakdown voltage island region, there is formed a circuit (not shown) for controlling an operation of high breakdown voltage pch-MOSFET 110. An n.sup.+ buried diffusion region 107b is formed between n.sup.- epitaxial layer 103b and p.sup.- silicon substrate region 101.
Conductive layers 141 forming field plates are formed above a region at which n.sup.- epitaxial layer 103a and p-type diffusion region 105 are in contact with each other and a region at which n.sup.- epitaxial layer 103b and p-type diffusion region 105 are in contact with each other.
An insulating layer 123 covering gate electrode layer 116, field plates 141 and others is formed on the surface of p-type silicon substrate 101. Insulating layer 123 is provided with a contact hole 123a reaching surfaces of source region 111 and n.sup.+ diffusion region 121, a contact hole 123g reaching a partial surface of gate electrode layer 117, a contact hole 123b reaching a partial surface of p-type diffusion region 113b, and a contact hole 123c reaching a partial surface of p-type isolation region 105.
A source electrode 125a is electrically connected to source region 111 and n.sup.+ diffusion region 121 through contact hole 123a. An aluminum interconnection layer 143 is electrically connected to gate electrode layer 117 through contact hole 123g. Source electrode 125a and aluminum interconnection layer 143 are electrically connected to elements formed at the high breakdown voltage island region.
A drain electrode 125b which is electrically connected to p-type diffusion region 113b through contact hole 123b is connected via a resistor 127 to an aluminum interconnection layer 125c which is electrically connected to p-type isolation diffusion region 105 through contact hole 123c.
When a control circuit in the high breakdown voltage island region negatively biases aluminum interconnection layer 143 with respect to source electrode 125a, the high breakdown voltage pch-MOSFET is turned on. Thereby, a current flows through resistor 127 and a voltage signal is generated. In this manner, the level shift-down function is achieved.
In the conventional semiconductor device described above, a high voltage is usually applied to n.sup.- epitaxial layers 103a and 103b shown in FIG. 21. In the high breakdown voltage pch-MOSFET formation region, therefore, a depletion region 150 defined by dotted line in FIG. 17 expands from regions such as a pn junction between n.sup.- epitaxial layer 103a and p-type isolation diffusion region 105 and a pn junction between p.sup.- silicon substrate region 101 and n.sup.- epitaxial layer 103a. The depletion region 150 expands into a majority of the high breakdown voltage pch-MOSFET formation region except for p-type diffusion region 113b, source region 111, n.sup.+ diffusion region 121, a portion of n.sup.- epitaxial layer 103a and a portion of n.sup.+ buried diffusion region 107a. Owing to the fact that a majority of high breakdown voltage pch-MOSFET 10A is taken into depletion region 150 as described above, high breakdown voltage pch-MOSFET 10A can achieve a high breakdown voltage.
Likewise, in the high breakdown voltage island region, depletion region 150 defined by dotted line expands from a pn junction between n.sup.+ epitaxial layer 103b and p-type isolation diffusion region 105 and a pn substrate region 101. This depletion region 150 has a configuration surrounding or extending around the high breakdown voltage island region. In general, an element such as an MOS transistor forming a circuit is not formed at the region in the high breakdown voltage island region through which depletion region 150 expands. This is because accurate operation would be difficult if such an element were taken into depletion region 150.
In the conventional semiconductor device shown in FIGS. 20 and 21, the potentials on source electrode 125a and aluminum interconnection layer 143 are controlled by a drive circuit in the high breakdown voltage island region. For this purpose, source electrode 125a and aluminum interconnection layer 143 extend from the high breakdown voltage pch-MOSFET formation region to the high breakdown voltage island region, so that they extend over p-type isolation diffusion region 105.
In general, p-type isolation diffusion region 105 surrounding n.sup.- epitaxial layer 103a is set to the lowest potential (e.g., the substrate potential). Thereby, n.sup.- epitaxial layer 103a and p-type isolation diffusion region 105 are always reversely biased, so that a depletion region of a high resistance exists at the pn junction between them, and this depletion region ensures a breakdown voltage.
However, the aluminum interconnection layer 143 and source electrode 125a, which are at a high potential and extend across this p-type isolation diffusion region 105, suppress extension of the depletion layer at the pn junction between p-type isolation diffusion region 105 and n.sup.- epitaxial layer 103a, resulting in reduction of the breakdown voltage.
In order to prevent reduction of the breakdown voltage, such methods have been employed that use insulating layer 123 having a increased thickness, that form a field plate 141 above the pn junction between n.sup.- epitaxial layer 103a and p-type isolation diffusion region 105 as shown in FIG. 21 for providing a shield against an electric field, and that employ a multilayer structure of the field plate in a floated state for stabilizing a surface electric field by capacity coupling.
However, as the breakdown voltage has been improved, it is now required to give a high insulating strength to insulating layer 123 itself between field plate 141 and aluminum interconnection layer 143 (or source electrode 125a). In order to ensure a high insulating strength, the film thickness of insulating layer 123 must be increased considerably, and therefore a long time is required for depositing insulating layer 123. As a result, a throughput decreases, and a process cost increases considerably.
The high breakdown voltage pch-MOSFET is isolated from the high breakdown voltage island region. This naturally increases a chip area.